Following lithographic exposure and prior to pattern developing, exposed lithographic layers, typically organic films, are thermally treated. The thermal treating (baking) of organic films is critical to the manufacturing process used for all integrated circuits. This process is called “post exposure bake” or PEB. Typical films include topcoat barrier layers (TC), topcoat antireflective layers (TARC), bottom antireflective layers (BARC), imaging layers (PR or photoresist) and sacrificial and barrier layers (hard mask) for etch stopping.
The PEB process time and temperature are used to define the characteristics of the circuit features prior to etching the feature into the substrate. By-products of the PEB process are sublimation products (solids) and out-gassing (liquid) materials. These byproducts can build up on the interior of the bake chamber and in the exhaust lines causing defects to fall onto the wafer in process. Typically, a cleaning of the bake system is required when these byproducts build up to certain levels. These methods may not be sensitive enough in future designs to meet sub 32 nm (nanometer) processing requirements. Minimizing defects during wafer processing will continue to be a critical path to attaining cost effective manufacturing of advanced semiconductor devices. Hard particles can block etch processes causing electrical “open” or “short” in the circuit. In lesser size and if fortunate with the location on the device, the hard particle may only create fatal perturbations in the active features' critical dimension (line/space or contact hole).
Advanced lithography applications use acid catalyzed chemically amplified resists to meet both sensitivity and resolution requirements. The quality of the resist pattern is impacted by the initial vertical distribution of photo acid generator (PAG) in the polymeric film after spin coating as well as the acid diffusion length during the post-exposure bake. It has been demonstrated in the literature that an electric field can be used to enhance the mobility of acid (H+) in the direction of the field during the post-exposure bake process. However, the literature demonstration involves the direct contact of a metal plate to the imaging resist. The contact between the metal plate and a resist surface in a hot plate can lead to higher defect levels due the transfer of particles to the metal plate or physical deformation of the image film, which makes the process less desirable for high volume manufacturing. This patent proposes the use of a novel monopole electrostatic chuck design as a means to generate charge on a semiconductor wafer, which produces an electric field across a resist without the direct contact of a top electrode.
It is anticipated contact with electrode will continue to provide problems.